1. Field of the Technology
The present application relates generally to the fields of electronic circuits, microelectronics, and radio frequency (RF) integrated circuit (IC) design, and more particularly to a low noise amplifier (LNA) which provides high signal gain with low power consumption by sharing a bias current among active devices of the LNA.
2. Description of the Related Art
A fundamental challenge in the design of a low noise amplifier (LNA) in an integrated circuit (IC) with a relatively small current consumption is to achieve a sufficient transconductance of the active devices for determining its gain and noise performance. The trade-offs between the signal gain, the noise figure, and the bias current are especially difficult with Complementary Metal-Oxide Semiconductor (CMOS) LNAs due to the inherent low transconductance of Metal-Oxide Semiconductor Field Effect Transistors (MOSFETs). For a constant current draw, the performance of high frequency LNAs can be improved by resonant load peaking using on-chip or external inductors. This approach, however, is not the most cost-effective due to the silicon area penalty or increased bill-of-material. In highly-integrated radio frequency (RF) communication transceivers, fully differential circuit topologies and signals are generally advantageous with respect to noise immunity, suppression of troublesome second-order spurious responses, and the grounding reference of sensitive RF modules. The performance advantages of differential RF circuits are, in most cases, a trade-off with the resulting increase in power consumption and larger die size. In cost-effective RF transceivers, package pins and external coupling networks are often shared by the receiver LNA input and the transmitter power amplifier output ports. In such transceivers, another desirable characteristic for a robust, low voltage, and low power amplifier design is a reasonably low and well-controlled impedance from the standpoint of the LNA input(s). As apparent, compact and robust differential LNA designs with high performance at low power consumption are highly desirable.
An established technique to achieve lower power amplification is “current reuse,” where a direct current (DC) bias current is recycled through several active devices. For example, U.S. Pat. No. 5,721,500 to Karanicolas describes a current reuse technique which effectively doubles the transconductance of a single stage of the amplifier without increasing the bias current. The transistors M1 and M2 of the '500 patent are utilized to essentially form a digital inverter which is biased for a large gain by the negative feedback loop. The key to the design in the '500 patent is that, given the same bias current, the effective transconductance of the amplifier is (gm1+gm2), as opposed to simply gm1 in the case that transistor M2 were omitted. This circuit has some drawbacks, such as high input and output impedances which require external matching networks in order to match to well-accepted impedance levels (e.g. 50 ohms). The high impedance nodes also make the circuit sensitive to capacitive parasitics. The circuit also requires a DC feedback network to define the operating points of the transistors. Finally, the design is inherently a single-ended circuit topology which is not always optimal from the standpoint of noise immunity in highly integrated designs.
Single-ended LNA topologies which provide current-reuse to achieve high transconductance are described in the prior art. One common drawback of these circuits is the large number of inductors required for impedance matching and signal transfer purposes. The use of such inductors results in either a prohibitively large silicon area for IC design or a large number of external components. For example, in U.S. Pat. No. 6,556,085 to Ick Jin Kwon et al., several single-ended LNA topologies employ current-reuse to achieve high transconductance. The open literature also teaches designs which utilize current-reuse cascading techniques, such as “A 5.7 GHz 0.18 μm CMOS Gain-Controlled Differential LNA With Current Reuse for WLAN Receiver,” Che-Hong Liao and Huey-Ru Chuang, IEEE Microwave and Wireless Component Letters, Vol. 13, No. 12, December 2003; “A 22-mW 435-MHz Differential CMOS High-Gain LNA For Subsampling Receivers,” Te-Hsin D. Huang et al., IEEE International Symposium on Circuits and Systems (ISCAs) 2002; and “Design of a 5.7 GHz 0.18 μm CMOS Current-Reused LNA For An 802.11A WLAN Receiver,” Liang-Hui Li and Huey-Ru Chuang, National Cheung Kung University, Taiwan, Microwave Journal, February 2004. The feedback, common-gate hybrid differential LNA circuit topology used by the Berkeley Wireless Research Center (USA) and presented by Stanley Wang in “RF Circuits & Antennas for <1 GHz UWB” on Jun. 12 2003, also employs a current-reuse technique and signal coupling scheme. In particular, the LNA presented by Stanley Wang combines shunt-series feedback and common-gate amplifier topologies by stacking a p-channel MOSFET (PMOS transistor) on top of an n-channel MOSFET (NMOS transistor). Still, however, better noise performance and higher design flexibility for an LNA may be achieved.